1. Field of the Invention
The invention relates to the process of fabricating semiconductor chips. More specifically, the invention relates to a method and an apparatus for performing optical proximity correction (OPC) on selected trim-level segments that do not abut features to be printed on the integrated circuit.
2. Related Art
Recent advances in integrated circuit technology have largely been accomplished by decreasing the feature size of circuit elements on a semiconductor chip. As the feature size of these circuit elements continues to decrease, circuit designers are forced to deal with problems that arise as a consequence of the optical lithography process that is typically used to manufacture integrated circuits. This optical lithography process begins with the formation of a photoresist layer on the surface of a semiconductor wafer. A mask composed of opaque regions, which are generally formed of chrome, and light-transmissive clear regions, which are generally formed of quartz, is then positioned over this photoresist layer. (Note that the term xe2x80x9cmaskxe2x80x9d as used in this specification is meant to include the term xe2x80x9creticle.xe2x80x9d) Light is then shone on the mask from a visible light source, an ultraviolet light source, or more generally some other type of electromagnetic radiation together with suitably adapted masks and lithography equipment.
This light is reduced and focused through an optical system containing a number of lenses, filters and mirrors. The light passes through the clear regions of the mask and exposes the underlying photoresist layer. At the same time, the light is blocked by opaque regions of the mask, leaving underlying portions of the photoresist layer unexposed.
The exposed photoresist layer is then developed, through chemical removal of either the exposed or non-exposed regions of the photoresist layer. The end result is a semiconductor wafer with a photoresist layer having a desired pattern. This pattern can then be used for etching underlying regions of the wafer.
Phase Shifting
As feature sizes continue to decrease, phase shifters are often incorporated into masks to achieve line widths that are smaller than the wavelength of the light that is used to expose the photoresist layer. During phase shifting, destructive interference caused by two adjacent clear areas on a phase shifting mask (PSM) is used to create an unexposed area on the photoresist layer. This is accomplished by exploiting the fact that light passing through a mask""s clear regions has a phase that is a function of the distance the light travels through the mask material. By placing two clear areas adjacent to each other on the mask, one of thickness t1 and the other of thickness t2, one can obtain a desired unexposed area on the underlying photoresist layer caused by destructive interference. By varying the thickness t1 and the thickness t2 appropriately, the light exiting the material of thickness t2 is 180 degrees out of phase with the light exiting the material of thickness t1. Phase shifting is described in more detail in U.S. Pat. No. 5,858,580, entitled xe2x80x9cPhase Shifting Circuit Manufacture Method and Apparatus,xe2x80x9d by inventors Yao-Ting Wang and Yagyensh C. Pati, filed Sep. 17, 1997 and issued Jan. 12, 1999.
Optical Proximity Correction
Optical proximity correction (OPC) is also used to improve printing of a layout. During the OPC process, additional features, such as xe2x80x9chammerheads,xe2x80x9d are often added onto features, such as line ends. The goal of OPC is to modify the layout such that the printed image of the modified layout more closely resembles the original layout. More generally, for an original layout T, OPC produces a modified layout Txe2x80x2 such that the printed image of Txe2x80x2 more closely resembles T. Additionally, the term OPC is used generically to refer to all types of proximity correction
In some cases, OPC is applied to both a phase shifting mask as well as a trim mask. In some embodiments, the approach of U.S. patent application Ser. No. 10/082,697 entitled xe2x80x9cOptical Proximity Correction For Phase Shifting Photolithographic Masksxe2x80x9d having inventors Pierrat et. al., and filed 25 Feb. 2002 are used. For example, the top portion of FIG. 1 illustrates the use of that approach for a target polysilicon line 104 to be printed using phase shifting. The top portion of FIG. 1 illustrates the original layout along with one of the phase shifters, phase shifter 102, which would be located on a dark field alternating aperture phase shifting mask. The phase shifter 102 is placed to abut a portion of the polysilicon line 104. The bottom portion of FIG. 1 illustrates a corresponding trim mask 106 that protects the portions of the polysilicon line 104 to being printed with the phase shifting mask and defines the remainder of the line. In the example illustrated in FIG. 1, OPC is applied to segments 108-110 on the phase shifting mask that abut polysilicon line 104. (Note that evaluation points for the OPC operation are represented by crosses in FIG. 1.) OPC is also applied to segments 111-112 on the trim mask 106 that abut polysilicon line 104. Note also that the example in FIG. 1 has been highly simplified, to highlight the handling of OPC for phase shifted structures.
Design Process
A brief discussion of where PSM and OPC fit in one common circuit design process may be helpful. Masks to be used in wafer fabrication process are the final result of the design process. The process starts when a circuit designer produces a design in VHDL, or some other hardware description language. VHDL is an acronym for VHSIC Hardware Description Language. (VHSIC is a Department of Defense acronym that stands for very high-speed integrated circuits.) The VHDL standard has been codified in Institute for Electrical and Electronic Engineers (IEEE) standard 1076-1993.
The design then feeds through a layout system that performs a number of functions, such as synthesis, placement and routing and verification. The result is an integrated circuit (IC) layout, which is in the form of a hierarchical specification expressed in a format such as GDSII.
IC layout then passes into PSM and OPC post-processing systems, which can perform PSM conversion and proximity corrections.
The output of PSM and OPC post-processing system is a new IC layout. New IC layout subsequently passes into mask fabrication and inspection processes.
Wafer Fabrication Process
The produced masks can be used in wafer fabrication processes. The system starts by applying a photoresist layer to the top surface of a wafer. Next, the system bakes the photoresist layer. The system then positions the first mask over the photoresist layer, and exposes the photoresist layer through the first mask. Next, the system positions the second mask over the photoresist layer, and then exposes the photoresist layer through the second mask. In one embodiment of the invention, the first mask is a PSM mask and the second mask is a binary trim mask. However, note that the first mask and/or the second mask can include phase shifting regions. Next, the system optionally bakes the wafer again before developing the photoresist layer. Next, either a chemical etching or ion implantation step takes place before the photoresist layer is removed. (Note that in the case of a lift-off process, a deposition can take place.) Finally, a new layer of material can be added and the process can be repeated for the new layer.
Problems in Printing Cutouts
As integration densities continue to increase, it is becoming necessary to use phase shifters to define progressively more features within a layout. In fact, some integrated circuits are beginning to be fabricated using a xe2x80x9cfull phasexe2x80x9d tape out methodology in which substantially all of the features in a layout are defined by phase shifters. However, the widespread use of phase shifters often leads to side-effects. For example, in FIG. 2, phase shifters 206 and 208 (which are of opposite phase) are used to define polysilicon regions 202 and 204. Unfortunately, the phase transition between phase shifters 206 and 208 results in an unexposed region 210 between polysilicon regions 202 and 204. This unexposed region 210 will cause unintended bridging between polysilicon regions 202 and 204. In order to remedy this problem, a subsequent exposure through a cutout 214 in trim 212 of trim mask 220 can be used to expose the unexposed region 210.
However, if the cutout 214 in trim 212 is too small, it may not allow sufficient light through to completely erase unexposed region 210. Moreover, conventional OPC may not help to alleviate this problem, because conventional OPC operates only on the top and bottom edges of cutout 214, which abut polysilicon regions 202 and 204. Adjusting only these edges may not allow sufficient light through to completely erase unexposed region 210.
What is needed is a method and an apparatus for alleviating the above-described exposure problem associated with cutouts on the trim mask.
One embodiment of the invention provides a system that performs optical proximity correction (OPC) on selected segments on a trim mask used in fabricating an integrated circuit. Upon receiving the trim mask, the system identifies selected segments on the trim mask that do not abut any feature to be printed on the integrated circuit. Next, the system performs a number of OPC operations. The system performs a first OPC operation on the selected segments to correct the selected segments. The system also performs a second OPC operation to correct segments on the trim mask that do abut features to be printed on the integrated circuit. The system additionally performs a third OPC operation on an associated phase shifting mask to correct segments that abut features to be printed on the integrated circuit. (Note that the first, second and third OPC operations can be performed separately or at the same time.)
In a variation on this embodiment, for a given selected segment, the first OPC operation attempts to ensure a pre-specified intensity level at an evaluation point on the given selected segment. This pre-specified intensity level can be different than a feature-defining intensity level that is associated with a resist trigger that defines printed edges of features within the integrated circuit. Moreover, the pre-specified intensity level can include a range of intensity levels that suffice to erase underlying features on the integrated circuit.
In a variation on this embodiment, identifying the selected segments involves identifying segments associated with a set of cutouts on the trim mask.
In a further variation, the set of cutouts includes cutouts that erase side-effects generated by transitions between zero-degree regions and 180-degree regions on an associated phase shifting mask.
In a further variation, the set of cutouts includes cutouts that define line ends.
In a variation on this embodiment, the selected segments on the trim mask are corrected based only on a contribution of the trim mask.
In a variation on this embodiment, the selected segments on the trim mask are corrected based on a contribution of the trim mask as well as a contribution of an associated phase shifting mask.
In a variation on this embodiment, identifying the selected segments involves identifying segments associated with features on the trim mask that are too small to expose an underlying photoresist layer.
In a variation on this embodiment, identifying the selected segments involves identifying segments associated with features on the trim mask that are so large that the features cause an overexposure of an underlying photoresist layer.
In a variation on this embodiment, identifying the selected segments on the trim mask involves identifying segments associated with assist features, wherein the assist features are non-printing features that assist in printing other features on the integrated circuit.